This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
- 5 stars58.91%
- 4 stars28.05%
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來自HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN的熱門評論
It's a nice course to exlpore VHDL and Verilog basics. Self learn is necessary. While coding any type of modelling is fine.
The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.
There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course
Professors were top-notch and clearly explained the pros and cons of each of the languages. I hope I could meet them in person.