本課程是 FPGA Design for Embedded Systems 專項課程專項課程的一部分

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Timothy Scherr 另外 +1 位授課教師

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隸屬於 Master of Science in Electrical Engineering 學位
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FPGA Design for Embedded Systems 專項課程科罗拉多大学波德分校

課程信息

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This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design.   It uses natural learning processes to make learning the languages easy.  Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs.  Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained.  After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

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第 2 門課程（共 4 門）

FPGA Design for Embedded Systems 專項課程

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完成時間大約為36 小時

英語（English）

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您將獲得的技能

Writing Code in Verilog
Simulating FPGA Designs
Designing FPGA Logic
Designing Test Benches
Writing code in VHDL

可靈活調整截止日期

根據您的日程表重置截止日期。

可分享的證書

完成後獲得證書

100% 在線

立即開始，按照自己的計劃學習。

第 2 門課程（共 4 門）

FPGA Design for Embedded Systems 專項課程

中級

完成時間大約為36 小時

英語（English）

對員工進行熱門技能培訓能否為您的公司帶來益處？

體驗 Coursera 企業版

授課教師

授課教師評分

4.24/5 （194 個評分）

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Electrical, Computer, and Energy Engineering

82,229 個學生

5 門課程

Benjamin Spriggs

Lecturer and Scholar of Engineering Practice

Electrical, Computer, and Energy Engineering

27,130 個學生

1 門課程

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科罗拉多大学波德分校

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此課程隸屬於科罗拉多大学波德分校提供的 100% 在線 Master of Science in Electrical Engineering。如果您被錄取參加全部課程，您的課程將計入您的學位學習進程。

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內容評分82%（1,414 個評分）

週

週 1

完成時間為 8 小時

Basics of VHDL

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

完成時間為 8 小時

10 個視頻（總計 48 分鐘）, 3 個閱讀材料, 6 個測驗

10 個視頻

Introduction to Hardware Description Languages for FPGA Design4分鐘

Why Learn VHDL?1分鐘

FPGA Design Flow3分鐘

Intro to VHDL: Finite State Machine3分鐘

How to speak VHDL, first phrases6分鐘

VHDL Assignments, Operators, Types3分鐘

VHDL Rules and Syntax, Interface Ports3分鐘

VHDL in ModelSim: Download and Install3分鐘

VHDL in ModelSim: Adding to your Toolkit6分鐘

Submitting VHDL Programming Assignments11分鐘

3 個閱讀材料

Hardware Description Languages for FPGA Design Assessment Strategy10分鐘

Misson 2-001: Week 1 Readings2小時

Files for Week 1 Programming Assignments10分鐘

2 個練習

VHDL Find the Code Errors30分鐘

Module 1 Quiz30分鐘

週

週 2

完成時間為 12 小時

VHDL Logic Design Techniques

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

完成時間為 12 小時

10 個視頻（總計 52 分鐘）, 2 個閱讀材料, 6 個測驗

10 個視頻

Learning to speak VHDL (Intro)1分鐘

Combinatorial Circuits4分鐘

Synchronous Logic: Latches and Flip Flops4分鐘

Synchronous Logic: Counters and Registers6分鐘

Buses and Tristate Buffers3分鐘

Modular Designs: Components, Generate and Loops in VHDL3分鐘

Test Benches in VHDL: Combinatorial8分鐘

Test Benches in VHDL: Synchronous5分鐘

Memory in VHDL7分鐘

Finite State Machines in VHDL8分鐘

2 個閱讀材料

Week 2 Readings2小時

Files for Week 2 Programming Assignments10分鐘

1 個練習

Module 2 Quiz30分鐘

週

週 3

完成時間為 7 小時

Basics of Verilog

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

完成時間為 7 小時

9 個視頻（總計 92 分鐘）, 2 個閱讀材料, 6 個測驗

9 個視頻

Verilog for fun and profit (intro)3分鐘

Your First Verilog phrase11分鐘

Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12分鐘

Verilog Statements and Operators16分鐘

Verilog Modules, Port Modes and Data Types10分鐘

Verilog Structure10分鐘

Testing with ModelSim5分鐘

Verilog Evaluation11分鐘

Submitting Verilog Programming Assignments10分鐘

2 個閱讀材料

Week 3 Readings1 小時 10 分

Files for Week 3 Programming Assignments10分鐘

2 個練習

Verilog Find the Errors20分鐘

Module 3 Quiz30分鐘

週

週 4

完成時間為 10 小時

Verilog and System Verilog Design Techniques

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.

完成時間為 10 小時

10 個視頻（總計 48 分鐘）, 2 個閱讀材料, 6 個測驗

10 個視頻

Learning to speak Verilog (intro)3分鐘

Combinatorial Circuits5分鐘

Synchronous Logic: Latches and Flip Flops3分鐘

Synchronous Logic: Counters and Registers5分鐘

Buses and Tristate Buffers3分鐘

Modular Design in Verilog3分鐘

Testbenches in Verilog7分鐘

Testbenches in Verilog II2分鐘

Memory with Verilog4分鐘

Verilog Finite State Machines7分鐘

2 個閱讀材料

Week 4 Readings15分鐘

Files for Week 4 Programming Assignments10分鐘

1 個練習

Module 4 Quiz30分鐘

審閱

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144 條評論

5 stars
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4 stars
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3 stars
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2 stars
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1 star
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來自HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN的熱門評論

由 SS 提供2022年5月28日

It's a nice course to exlpore VHDL and Verilog basics. Self learn is necessary. While coding any type of modelling is fine.

由 HH 提供2020年5月14日

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

由 DR 提供2022年2月20日

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course

由 JV 提供2021年2月23日

Professors were top-notch and clearly explained the pros and cons of each of the languages. I hope I could meet them in person.

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關於 FPGA Design for Embedded Systems 專項課程

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:

Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.

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