This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
- 5 stars58.53%
- 4 stars28.25%
- 3 stars7.11%
- 2 stars3.04%
- 1 star3.04%
來自HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN的熱門評論
The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.
The course helped in showing the different styles of the Verilog and VHDL coding.
Understood the advantages of Verilog and VHDL in real life applications
It's a nice course to exlpore VHDL and Verilog basics. Self learn is necessary. While coding any type of modelling is fine.
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .