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Learner Reviews & Feedback for Hardware Description Languages for FPGA Design by University of Colorado Boulder

4.4
stars
549 ratings

About the Course

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Top reviews

BM

Jul 26, 2023

Absolutely the best course I've taken! It was incredibly comprehensive, and I learned so much from it. Highly recommended for anyone looking to delve into FPGA and hardware design.

JS

Jun 6, 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

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126 - 150 of 154 Reviews for Hardware Description Languages for FPGA Design

By Uzair A

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Oct 9, 2020

its a very nice course. Its help me a lot to understand the basic of fpga.

By Apoorva S

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May 25, 2020

A very engaging course to do for beginners having fundamentals strong.

By Yuvraj S R

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May 18, 2020

Explanations are not that good for some circuits like memory

By Sourav N

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Sep 18, 2020

There should have been more examples of problems.

By Mohamed C

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Apr 30, 2020

a big thank you to all the professiors

By Engels M

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Dec 3, 2021

Concise, practical and useful

By Prakash K R

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Jun 24, 2020

It should be more elaborative

By Arun L

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Jul 13, 2023

Valuable and Informative

By Anas A I

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Sep 29, 2022

cours très intéressant

By عبدالرحمن خ ا

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Sep 16, 2022

i love this course

By TUMMALAPALLI S V N S

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Jun 7, 2020

BEST FOR THE BASIC

By Sai D

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Aug 4, 2023

Good

By J S

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Aug 5, 2020

good

By Artur K

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Oct 9, 2022

The course is split into 2 weeks of VHDL and 2 weeks of Verilog, with two different instructors. Unfortunately, the first 2 weeks are really dragging down the quality of the course. They are riddled with bad explanations, omissions, and plain errors throughout. I'd go as far as to say the student learns the contents of those weeks because of the reading materials (which do a good job explaining what's actually going on), and despite the instructor video lectures , which are just leading the student astray.

The programming assignments in both parts of the course leave a lot to be desired with regard to the quality of specifications. They frequently don't explain how the list of control signals is supposed to interact, which signals are active high vs. active low, whether they are assumed to be synchronous or async etc.

I'm missing coverage of how exactly different subtle choices of writing the code affects the synthesis of the FPGAs in various ways, by way of examples that show what happens in those cases.

By Adriel K

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Mar 16, 2022

The course is OK, but the videos are terrible. The presenters do nothing more than just read the slides as they appear, which are sometimes just a page of code. In the VHDL section, I believe the presenter is seeing the material for the first time. I ended up just turning the audio off and treating the videos as a slide deck, which worked quite well. The assignments were fun.

By Julien T

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Dec 7, 2021

Interesting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...

By Islam E

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May 31, 2020

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

By Harsh A

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Jun 15, 2020

Verilog part is explained very well but VHDL part completely unsatisfied.

By Sachin A

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Apr 21, 2020

Very introductory. Verilog and VHDL exercises are copied.

By Sakshat R

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May 28, 2020

Innovative teaching, but very poor assignments

By Samuel C

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Aug 14, 2020

A decent introduction to HDL.

By Pushkar A

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Sep 30, 2020

Teaching could be better.

By JYOTI S S

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Jul 11, 2021

good

By Nur Y Y

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Sep 27, 2022

Assignments are not clear and I cannot open assignment files. Because of this I cannot finish the course. Also, ModelSim download link was not working. I have a lot of trouble about download.

By Ethan R

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Apr 11, 2020

The highlight of this course was the recommended reading materials.